每日资讯Daily Notes
从设备需求到 CFET 模块：把产能信号与可制造性证据分开确认From equipment demand to CFET modules: separate capacity signals from manufacturability evidence
依据 ASML 与 imec 的公开资料整理。行业与研发信号不替代目标项目的工艺放行证据。Based on public materials from ASML and imec. Industry and R&D signals do not replace project-specific release evidence.
设备需求：订单能见度不是某条工艺线已经可用Equipment demand: order visibility is not readiness of a specific process flow
ASML 在 10 月 14 日发布的 2026 年第三季度业绩中称，客户正提高中短期设备需求预测，并已出现面向 2029 和 2030 年的订单兴趣；公司同时评估进一步增加 2028 年产能。这是光刻设备生态与供应节拍的背景信号。对具体项目而言，它不等同于某一层的设备时间、掩模/版图、光刻胶、对准策略、缺陷控制或交付周期已经获得确认。In its October 14 Q3 release, ASML said customers are raising near- and mid-term equipment-demand forecasts, with interest in orders for 2029 and 2030, while the company evaluates additional 2028 capacity. That is ecosystem context, not confirmation of tool time, mask/layout, resist, alignment, defect control or delivery for a specific layer.
CFET 路线：标准单元推演仍要回到模块集成CFET roadmap: standard-cell exploration still returns to module integration
imec 近期技术更新讨论了面向 A7 及后续节点的 CFET 标准单元选择，包括 split-gate / common-gate 器件选项、SRAM 单元和后段布线可达性。该类设计—技术协同研究可帮助识别栅堆叠、背面接触、互连与版图之间的耦合；但任何结构的可制造性仍需由目标材料堆栈、热预算、对准、刻蚀/沉积、截面量测和电学测试逐批验证。A recent imec update discusses CFET standard-cell options for A7 and beyond, including split-gate/common-gate devices, SRAM cells and BEOL routability. Such DTCO work reveals coupling among gate stacks, backside contacts, interconnect and layout; manufacturability still needs lot-specific proof across stack, thermal budget, alignment, etch/deposition, cross-section metrology and electrical testing.
一个工艺观察Process Note
把“需求背景”与“可放行证据”放在两张表里Keep demand context and release evidence in separate tables
素微编辑观察：产能展望、路线图和论文/技术更新适合形成风险清单，而不是直接形成制造承诺。项目表应单独锁定基底与薄膜、版图版本、关键尺寸、前后段工序、工艺版本、量测位置、抽样数量和接受准则；再将设备可用性、排期与资源方书面确认附到同一版本。这样行业变化不会掩盖项目真正的放行条件。素微 editorial note: capacity outlooks, roadmaps and technical updates make useful risk lists, not manufacturing commitments. A project sheet should separately lock stack, layout revision, critical dimensions, upstream/downstream steps, recipe revision, metrology sites, sample count and acceptance criteria; then attach written tool, schedule and resource confirmation to that version.
项目准备提醒Project Prep
提交先进图形或异构集成需求时，先写出最小验证闭环For advanced patterning or heterogeneous integration, state the minimum validation loop first
请写明目标结构与允许偏差、材料堆栈和热预算、版图/对准标记版本、预期曝光或沉积/刻蚀链、必须量测的 CD、膜厚、对准和电学项目，以及失效判定和返工边界。公开资讯可协助提出检查项，但不替代资源方对具体工具、工艺窗口、良率、排期和交期的书面确认。State target structures and tolerances, stack and thermal budget, layout/alignment-mark revision, expected exposure or deposition/etch chain, required CD/thickness/alignment/electrical measurements, and failure/rework boundaries. Public news helps frame checks; it does not replace written confirmation of tools, windows, yield, schedule or delivery.
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