专业词入口Topic Entry
晶圆级封装（WLP）把互连、保护、再布线、凸点或模塑等环节尽可能留在晶圆阶段完成。它不是一个可直接报价的单一工序：晶圆尺寸与厚度、die map、I/O、RDL/TSV、材料体系、翘曲、切割和测试接口要一起确认，才能判断适用路线。Wafer-level packaging keeps interconnect, protection, redistribution, bumps or molding at wafer scale where possible. It is not a single quotable step: wafer format, die map, I/O, RDL/TSV, material stack, warpage, singulation and test interfaces must be reviewed together.
需要缩短互连、降低模组厚度、提高 I/O 密度或在晶圆阶段完成批量封装评估的项目；常见于传感器、MEMS、光电、芯粒验证和扇出型封装前期路线判断。Projects seeking shorter interconnects, lower package height, higher I/O density or wafer-scale assembly assessment; common in sensors, MEMS, photonics, chiplet trials and fan-out route studies.
晶圆材料、直径、厚度和背面状态；die map、划片道与良率信息；pad map、I/O/pitch、金属堆栈；是否已有 RDL、凸点、TSV、键合或模塑设想；允许热预算、翘曲边界、目标数量、测试方式和交付状态。未定参数应明确标为待工艺平台确认。Provide wafer material, diameter, thickness and backside state; die map, streets and yield data; pad map, I/O/pitch and metallurgy; any RDL, bump, TSV, bonding or molding assumption; thermal ceiling, warpage limit, quantity, test method and delivery state.
晶圆翘曲、颗粒和表面污染会影响光刻、键合或贴装窗口；RDL 与凸点的共面性、热膨胀失配、薄晶圆搬运、切割应力和已知良品测试策略都可能改变路线。涉及 Fan-Out、细 pitch 或可靠性指标时，必须由接收方确认设备能力和认证计划。Warpage, particles and surface contamination affect lithography, bonding and assembly windows. RDL/bump coplanarity, CTE mismatch, thin-wafer handling, singulation stress and known-good-die strategy can all change the route. Fan-out, fine-pitch and reliability targets require receiver-side capability and qualification confirmation.
推荐下一步Next Step
请把晶圆版本与照片、die/pad map、关键 pitch、目标 RDL 或凸点状态、热预算、翘曲/厚度限制、测试和数量放入同一份资料。素微 可协助整理为可由封装平台核对的需求清单，不替代接收方的封装设计签核、制程认证或可靠性承诺。Put wafer revision and photos, die/pad map, critical pitch, intended RDL or bumps, thermal limits, warpage/thickness constraints, tests and quantity in one package. 素微 can organize it for platform review, not replace package sign-off, qualification or reliability commitments.
提交晶圆级封装需求Submit WLP request需要 I/O 重排、扇出互连或晶圆级布线时，先单独确认层数、介质、线宽线距与焊盘接口。For I/O redistribution, fan-out interconnect or wafer-level routing, define layers, dielectrics, CDs and pad interfaces first.
查看 RDL 再布线层准备Open RDL guide若晶圆完成后需要 die-to-carrier 互连，应并行确认凸点、对准与回流边界。If die-to-carrier interconnect follows wafer processing, confirm bumps, alignment and reflow limits in parallel.
查看倒装焊封装准备Open flip-chip guide涉及通孔、临时键合、背面减薄或背面金属时，应把 TSV 路线与 WLP 交接点分开确认。For vias, temporary bonding, thinning or backside metal, separate TSV-route and WLP handoff decisions.
查看 TSV 工艺需求Open TSV guide