适合什么需求Good For
芯片垂直互连、MEMS 与 ASIC 集成、传感器背面引出、硅中介层、微流控/光电封装接口，以及需要缩短互连或释放正面布线空间的验证项目。Vertical interconnects, MEMS–ASIC integration, backside routing, silicon interposers, and sensor, microfluidic or photonic packaging interfaces.
专业词入口Topic Entry
TSV 硅通孔，先把“孔怎么做、怎么绝缘、怎么连通”拆成可验收的工艺链。For TSV, turn via formation, isolation and interconnect into an acceptance-ready process chain.
TSV（Through-Silicon Via）不是只有深硅刻蚀：通孔直径与深度、绝缘衬层、阻挡层/种子层、金属填充、背面减薄和后段互连相互耦合。先把截面、热预算与电学目标讲清，才方便判断可行路线和资源接口。A TSV is more than a deep silicon etch. Via geometry, dielectric liner, barrier/seed, fill, thinning and interconnect are coupled; define cross-section, thermal budget and electrical targets first.
需要准备什么Prepare First
截面示意与 GDS、硅片厚度及正背面膜层、孔径/孔距/阵列开口率、目标深度与是否贯穿、允许的侧壁和 scallop、绝缘材料、金属体系、最高温度、背面减薄及测试焊盘方案。Cross-section and GDS, wafer stack, via CD/pitch/open area, depth and through-etch need, wall/scallop limits, dielectric, metal stack, thermal budget, thinning and probe-pad plan.
常见风险Common Risks
高深宽比造成刻蚀、衬层或填充不均；Bosch 侧壁形貌影响覆盖；绝缘层针孔导致漏电；种子层连续性不足；填充空洞、热应力、背面露铜和减薄后翘曲都会影响成品率。High aspect ratio can cause nonuniform etch, liner or fill; sidewall profile, dielectric pinholes, discontinuous seed, voids, stress, copper reveal and thinning warp all affect yield.
推荐下一步Next Step
先发截面图、孔阵列版图和目标电学指标，再拆分 TSV 工艺窗口。Send the cross-section, via-array layout and electrical targets before defining the TSV window.
建议同步说明目标电阻/漏电、耐压或频率要求、允许的空洞与侧壁标准、是否需截面 SEM 或四线法测试。微纳Hub 会先协助区分通孔形成、绝缘、金属化、减薄和封装接口，避免只按“打孔”询价而遗漏后段风险。Include resistance, leakage, voltage or frequency targets; void and wall criteria; and whether cross-section SEM or four-wire testing is required. We first separate formation, isolation, metallization, thinning and package interfaces.
提交 TSV 硅通孔需求Submit TSV request先看深硅刻蚀Start with DRIE
通孔形成前，先确认深宽比、开口率、掩膜余量和背面保护。Confirm aspect ratio, open area, mask budget and backside protection before via formation.
查看 DRIE 深硅刻蚀准备Open DRIE guide高深宽比绝缘层Conformal Liner
通孔绝缘层需结合深宽比和耐压要求判断共形覆盖与验收截面。Choose conformal coverage and cross-section acceptance from aspect ratio and voltage needs.
查看高深宽比 ALD 覆盖Open ALD conformality guide电学连通验收Electrical Check
低阻通孔与互连建议在测试方案中明确接触方式、量程和四线法边界。Define probing, range and four-wire boundaries for low-resistance vias and interconnects.
查看开尔文四线电阻测试Open four-wire test guide