专业词入口Topic Entry

倒装焊封装，先把凸点、对准、热预算和验收接口一起讲清。For flip chip, define bumps, alignment, thermal budget and acceptance together.

倒装焊不只是把芯片翻过来贴到基板上。焊盘金属与凸点体系、pitch、共面性、基板或中介层、对准精度、回流温度、底填、翘曲和电学测试会共同决定可行性。先把这些接口拆开，才方便封装平台核对路线。Flip-chip assembly is more than placing a die face-down. Pad and bump metallurgy, pitch, coplanarity, carrier or interposer, alignment, reflow temperature, underfill, warpage and electrical test jointly determine feasibility.

适合什么需求Good For

高密度 I/O、小型化模组、光电芯片、传感器阵列、RF/高速互连、芯粒验证，以及需要把芯片直接连接到载板、中介层或 PCB 的原型封装。High-density I/O, compact modules, photonic chips, sensor arrays, RF/high-speed interconnect, chiplet trials and prototype attachment to carriers, interposers or PCBs.

需要准备什么Prepare First

芯片尺寸和正反面照片、pad map 与 pinout、焊盘/凸点金属堆栈、凸点直径和 pitch、基板 Gerber 或焊盘图、目标对准精度、最高温度、是否底填、数量、测试方式与交付状态。未知项应标为待封装平台确认。Provide die size and views, pad map and pinout, pad/bump stack, bump diameter and pitch, carrier artwork, target alignment, temperature ceiling, underfill need, quantity, test method and delivery state.

常见风险Common Risks

氧化、污染、共面性不足或 pad/凸点尺寸偏差会造成开路、虚焊或桥连；芯片、基板与底填材料的热膨胀失配会带来翘曲和热循环风险。细 pitch、无铅体系和光电耦合项目还需单独确认设备能力、温度窗口与检测方案。Oxide, contamination, poor coplanarity or pad/bump variation can cause opens, non-wet or bridges; thermal-expansion mismatch can create warpage and cycling risk. Fine-pitch, lead-free and photonic projects need separate equipment, thermal-window and inspection review.

推荐下一步Next Step

先发芯片 pad map、基板焊盘图和温度/测试边界，再确认凸点与贴装路线。Send the die pad map, carrier layout and temperature/test limits before selecting the bump and assembly route.

请将芯片/基板版本、凸点或裸 pad 状态、I/O 编号、关键 pitch、允许热预算、是否需要底填、测试电流电压和样品数量放进同一份资料。微纳Hub 可协助整理为封装平台可核对的需求清单，不替代接收方的制程认证、失效分析或可靠性承诺。Put die/carrier revisions, bump or bare-pad condition, I/O IDs, critical pitch, thermal ceiling, underfill need, electrical conditions and quantity in one handoff. MN Fab Hub can organize a request for platform review, not replace qualification, failure analysis or reliability commitments.

提交倒装焊封装需求Submit flip-chip request

键合与封装入口Packaging Route

先把芯片、载板、材料和验收接口统一到一份需求里。Unify chip, carrier, material and acceptance interfaces first.

查看键合与封装工艺导航Open packaging route

引线键合封装Wire Bonding

若 I/O 密度和线弧空间允许，也可先比较引线键合的互连与测试准备。When I/O density and loop clearance permit, compare wire-bonding handoff needs.

查看引线键合封装准备Open wire-bonding guide

TSV 与背面互连TSV Interconnect

涉及硅通孔、背面减薄或晶圆级互连时，应先拆分 TSV 与倒装焊封装接口。For TSV, backside thinning or wafer-level interconnect, separate TSV and flip-chip interfaces early.

查看 TSV 硅通孔工艺需求Open TSV guide