每日轻资讯Daily Notes
从 EUV 光源到 InP 光子制造：今天三个小观察。From EUV light sources to InP photonics: three short notes.
网站资讯尽量保持轻量：看一个行业动向，顺手带一个工艺理解，再落到项目沟通里能用的提醒。A light note: one industry signal, one process angle and one practical reminder.
EUV 继续往“光源工程”深处走。EUV keeps moving deeper into light-source engineering.
NIST/CHIPS 近期公布对 xLight 的 1.5 亿美元最终激励，用于在 Albany Nanotech Complex 建设并验证自由电子激光 FEL 原型。对微纳加工来说，这个新闻的信号很清楚：先进光刻的瓶颈不只在曝光机，也在光源功率、效率、良率和整套生态。NIST/CHIPS announced a $150 million final award for xLight to build and demonstrate a free-electron laser prototype at Albany Nanotech Complex. The signal is clear: advanced lithography depends on source power, efficiency, yield and ecosystem readiness, not just scanners.
InP 光子制造被推到 AI 数据通道前台。InP photonics is moving to the front of AI data movement.
NIST/CHIPS 还发布了对 Coherent 最高 5000 万美元的意向支持，用于扩建德州 Sherman 的 150 mm InP 晶圆制造能力。InP 光子器件对应高速光互连，背后其实是 AI 数据中心里“数据搬运”的能耗和带宽问题。NIST/CHIPS also announced intent to support Coherent with up to $50 million to expand 150 mm InP wafer manufacturing in Sherman, Texas. InP photonic devices connect directly to bandwidth and energy limits in AI data centers.
会议议程显示：先进封装仍在升温。Event agendas show advanced packaging is still heating up.
SEMI 公布 SEMICON West 2026 将在 10 月回到旧金山，技术重点包括 Advanced Packaging and Heterogeneous Integration、AI Computing、Photonics 等方向；7 月的 Advanced Packaging Summit 2026 议程也覆盖 AI/HPC、功率模块、glass core substrate。封装已经很难只当“后道配套”来看。SEMI says SEMICON West 2026 returns to San Francisco in October with tracks including advanced packaging, heterogeneous integration, AI computing and photonics. Its July Advanced Packaging Summit agenda also covers AI/HPC, power modules and glass core substrates.
一个工艺提醒Process Reminder
涉及光子、封装或多层结构时，先把边界说出来。For photonics, packaging or multilayer structures, state the boundaries early.
如果项目涉及光刻、刻蚀、薄膜、InP/GaAs/Si 等材料，或需要和封装、引线、光耦合配合，建议先准备 GDS/DXF 或截图、关键尺寸、材料堆栈、加工面积、对准关系、后续封装方式、检测方式和不能承受的工艺限制。对方越早知道边界，越容易给出真实判断。For lithography, etch, films, InP/GaAs/Si materials or downstream packaging and optical coupling, prepare GDS/DXF or screenshots, critical dimensions, stack, area, alignment, packaging assumptions, metrology and process limits.