从光掩模、2D 材料到 3DIC：本周三个制造信号。From masks and 2D materials to 3DIC: three manufacturing signals.

今天的关键词不只是“更小线宽”，而是制造链条里每个环节都在往可量产、可验证、可集成的方向收紧。Today is less about smaller features alone, and more about manufacturing links becoming scalable, verifiable and integrable.

Intel 在加码先进光掩模产能。Intel is adding advanced photomask capacity.

Tom's Hardware 报道，Intel 已在 Santa Clara 的 Bowers Campus 启动光掩模设施扩建，目标覆盖 DUV、EUV 以及未来 High-NA EUV 所需的 6 英寸 reticle。对微纳加工的启发是：先进光刻不只看曝光机，mask 写入、OPC、清洗、寿命和周转速度也会影响真实交期。Tom's Hardware reports that Intel has started expanding mask operations at its Bowers Campus in Santa Clara for DUV, EUV and future High-NA EUV reticles. Advanced lithography depends on scanners, but also mask writing, OPC, cleaning, lifetime and turnaround.

2D 材料晶体管更靠近 300 mm 工艺线。2D-material transistors move closer to 300 mm process flows.

imec、ASML 和 TSMC 近期展示了基于 300 mm 工艺的 TMD 晶体管进展，EUV 图形化把沟道长度推进到 28 nm，并采用底部接触与覆盖式沉积栅的反向 TFT flow。新闻点不在“立刻商用”，而在 2D 材料正在被放到更像真实晶圆线的流程里验证。imec, ASML and TSMC showed 300 mm TMD transistor progress, using EUV patterning for 28 nm channels and a reverse TFT flow with bottom contacts and overlapping deposited gates. The key signal is lab-to-fab validation.

SiC 功率器件和封装场景继续扩展。SiC power devices keep expanding into harsh-use packaging.

NIST/CHIPS 公布与 I-Pulse 的 2.5 亿美元研发协议，聚焦高温、高电流、高压的 SiC 开关和脉冲功率应用。SiC 不是只做“材料片”，它后面连着外延、刻蚀、金属接触、热管理和耐冲击封装。NIST/CHIPS announced a $250 million R&D award with I-Pulse for high-temperature, high-current and high-voltage SiC switches. SiC projects quickly connect epitaxy, etch, contacts, thermal paths and rugged packaging.

一个行业观察Industry Note

先进封装的话题越来越像“前道工艺的延长线”。Advanced packaging is starting to look like an extension of front-end process work.

SEMI 7 月 Advanced Packaging Summit 的议程里，3DIC、TSV 高深宽比刻蚀、void-free 填充、介质沉积、chiplet gap fill 和 plasma dicing 都放在 AI 封装生产化语境下讨论。很多项目以前会把“做出图形”和“最后封装”分开想，现在最好从一开始就把厚度、台阶、对准、后续切割和电/光互连一起考虑。SEMI's July Advanced Packaging Summit agenda puts 3DIC, high-aspect-ratio TSV etch, void-free fill, dielectric deposition, chiplet gap fill and plasma dicing into an AI manufacturing context. Patterning, dicing and interconnect assumptions should be discussed together earlier.

项目准备提醒Project Prep

如果样品后面要封装或测试，别只给版图截图。If packaging or testing follows, do not send only a layout screenshot.

建议同步准备 GDS/DXF、关键尺寸、材料堆栈、膜厚、基底尺寸、对准层、是否要开窗或刻通、切割/解理道、焊盘或光耦合位置、预期检测方式。尤其是薄片、III-V、SiC 或多层结构，越早说明不能承受的温度、等离子体、清洗液和机械夹持限制，越容易避免返工。Prepare GDS/DXF, critical dimensions, stack, film thickness, substrate size, alignment layers, openings, cleaving streets, pads or optical coupling positions and metrology plans. For thin chips, III-V, SiC or multilayers, state thermal, plasma, chemical and handling limits early.

Intel 在加码先进光掩模产能。Intel is adding advanced photomask capacity.

2D 材料晶体管更靠近 300 mm 工艺线。2D-material transistors move closer to 300 mm process flows.

SiC 功率器件和封装场景继续扩展。SiC power devices keep expanding into harsh-use packaging.

先进封装的话题越来越像“前道工艺的延长线”。Advanced packaging is starting to look like an extension of front-end process work.

如果样品后面要封装或测试，别只给版图截图。If packaging or testing follows, do not send only a layout screenshot.

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