每日轻资讯Daily Notes
从 High NA EUV、量子光子集成到 300mm 量子芯片：今天三个工艺接口信号。From High NA EUV and quantum photonic integration to 300mm quantum chips: three process-interface signals.
今天的三条信息都指向同一个工程问题：先进器件从论文或单点验证走向可复制样片时，关键不只是结构尺寸，还包括光刻可制造性、异质材料对准和低温/光电测试链路。Today's three signals point to one engineering issue: when advanced devices move from papers or single demonstrations toward repeatable samples, the bottleneck is not only feature size. Lithography manufacturability, heterogeneous-material alignment and low-temperature or optoelectronic test flow all matter.
High NA EUV 第一次进入高量产逻辑产品节点。High NA EUV has entered a high-volume logic product milestone.
ASML 7 月 15 日宣布，Intel Foundry 已在 Intel 18A 的部分 Core Ultra Series 3 处理器层次中使用 ASML EXE High NA EUV 技术，相关层在 Oregon 完成 dual qualification，并以与 NXE 平台匹配的良率向客户出货。对光刻项目来说，这条信息的重点不是“所有层都会立刻换 High NA”，而是先进图形化正在进入更明确的层选择、overlay、产能和良率验证阶段。ASML announced on July 15 that Intel Foundry is using ASML EXE High NA EUV technology on selected Intel 18A layers for Core Ultra Series 3 processors. Those layers have been dual-qualified in Oregon, with customer shipments at yields matched to the NXE platform. For lithography projects, the useful point is not that every layer immediately moves to High NA. Advanced patterning is entering a more concrete phase of layer selection, overlay, throughput and yield qualification.
自对准异质集成降低量子光子接口损耗。Self-aligned heterogeneous integration reduces quantum-photonic interface loss.
Light: Science & Applications 7 月 15 日发表论文，展示把 diamond nanobeam 嵌入 TiO2 光子晶体和波导的自对准异质集成路线。流程包含电子束胶中定义反向图形、放入 diamond nanobeam、共形沉积 TiO2、回刻和去胶。它对微纳加工的启发很直接：异质光子器件常常不是单独做好两个材料再简单贴合，而要把机械定位、间隙、沉积覆盖性和后续刻蚀一起设计。A July 15 paper in Light: Science & Applications demonstrates a self-aligned route that embeds diamond nanobeams into TiO2 photonic crystals and waveguides. The process defines the inverse circuit in e-beam resist, inserts the diamond nanobeam, conformally deposits TiO2, back-etches and strips the resist. The fabrication lesson is direct: heterogeneous photonic devices are often not made by separately finishing two materials and attaching them later. Mechanical positioning, gap control, deposition conformality and downstream etch have to be co-designed.
300mm CMOS 兼容平台开始承载更大硅自旋量子比特阵列。A 300mm CMOS-compatible platform is carrying larger silicon spin-qubit arrays.
imec 和 Diraq 7 月 13 日宣布，在 imec 的 300mm CMOS 兼容硅自旋量子比特平台上实现并读出了 8 个 silicon MOS spin qubit 线性阵列。相比单个或两个量子比特演示，这类进展把问题推向更实际的制造接口：栅极堆叠、低温读出、布线密度、热负载、器件一致性和批量表征需要一起被纳入设计约束。Imec and Diraq announced on July 13 coherent operation and readout of an eight silicon MOS spin-qubit linear array fabricated on imec's 300mm CMOS-compatible silicon spin-qubit platform. Compared with one- or two-qubit demonstrations, this pushes the interface toward practical manufacturing: gate stacks, cryogenic readout, wiring density, thermal load, device uniformity and batch characterization have to be treated as shared constraints.
一个行业观察Industry Note
先进结构越来越像“工艺接口工程”，不是单一设备参数竞赛。Advanced structures increasingly look like process-interface engineering, not a single-tool race.
High NA EUV 关心哪些层值得引入新曝光平台；自对准异质集成关心材料和几何如何在同一流程里自动对准；300mm 量子芯片关心低温测试和可重复制造能否跟上器件规模。三者放在一起看，真正影响项目推进的常常是接口：版图层、材料堆叠、对准基准、刻蚀终点、接触 pad、测试温区和统计样本量。High NA EUV asks which layers justify a new exposure platform. Self-aligned heterogeneous integration asks how materials and geometry align within one process. 300mm quantum chips ask whether cryogenic test and repeatable fabrication can scale with device count. Taken together, the real project risk often sits at the interfaces: layout layers, material stacks, alignment marks, etch endpoints, contact pads, test temperature and sample statistics.
项目准备提醒Project Prep
做异质光子、量子器件或先进光刻样片时，先写“接口约束表”。For heterogeneous photonics, quantum devices or advanced lithography samples, write an interface-constraint table first.
建议在需求文件里补充：每一层的关键尺寸和容差、对准标记位置、材料厚度和最高温度、沉积是否需要共形覆盖、刻蚀是否允许过刻、电极 pad 与探针间距、光路耦合方向、低温或真空测试条件、每批需要多少颗器件做统计。这样微纳Hub 更容易把版图审查、工艺试片、外协资源和验收方式拆开判断。Add these items to the request file: critical dimension and tolerance for each layer, alignment-mark position, material thickness and maximum temperature, whether conformal deposition is required, whether over-etch is allowed, pad and probe pitch, optical coupling direction, low-temperature or vacuum test conditions, and device count for statistics. This helps 微纳Hub separate layout review, process coupons, external resources and acceptance criteria before quoting or fabrication.