每日轻资讯Daily Notes
从纳米光子电注入、硅光产能到晶圆探针卡：今天三个量产验证信号。From nanophotonic electrical injection and silicon-photonics capacity to wafer probe cards: three production-validation signals.
今天三条信息从器件结构、晶圆制造一路延伸到晶圆级测试。共同点是：能做出单个样品还不够，电学均匀性、工艺平台兼容性和可测试性必须在设计阶段一起定义。Today's signals run from device architecture through wafer manufacturing to wafer-level test. A single working sample is not enough: electrical uniformity, process-platform compatibility and testability must be defined together at design time.
UC Berkeley 用纳米柱触点实现不扰动光场的电注入。UC Berkeley uses nanopost contacts for electrical injection without disturbing the optical field.
UC Berkeley 与 Berkeley Lab 7 月 6 日介绍了一种室温电驱动纳米光子激光器：把导电纳米柱放在电磁场节点处，在保持光学模式的同时向数百个微小单元均匀供电。研究团队发现，主要限制并非光学设计，而是纳米柱尺寸变化带来的电流不均匀。这把关键尺寸控制从“能否成形”进一步推到“能否保持电学一致性”。UC Berkeley and Berkeley Lab reported a room-temperature electrically driven nanophotonic laser. Conductive nanoposts sit at electromagnetic-field nodes, feeding hundreds of cells while preserving the optical mode. The key limitation was not optical robustness but current nonuniformity caused by small nanopost variations.
Tower 扩充 300 mm 硅光、SiGe 与先进封装产能。Tower is expanding 300 mm silicon photonics, SiGe and advanced-packaging capacity.
Tower Semiconductor 7 月 14 日披露，在日本政府支持下推进双轨扩产，重点覆盖 300 mm 硅光子、SiGe 和先进封装。对项目方而言，扩产信号不只是“有更多产能”，也意味着版图规则、材料堆栈、晶圆级工艺、封装接口和量产测试需要落到同一平台约束中；早期原型若脱离目标产线规则，后续迁移成本会迅速放大。Tower Semiconductor disclosed a dual-track Japan expansion covering 300 mm silicon photonics, SiGe and advanced packaging. For project teams, added capacity also means aligning layout rules, material stacks, wafer processes, package interfaces and production test with the target platform.
FormFactor 新探针卡工厂把晶圆级测试能力推到供应链前台。FormFactor's new probe-card facility brings wafer-level test capacity to the foreground.
得克萨斯州政府 7 月 2 日宣布向 FormFactor 的新探针卡制造设施提供 2420 万美元支持，项目计划投入 1.4 亿至 1.7 亿美元。探针卡连接晶圆焊盘与测试系统，其针距、接触力、焊盘材料、温度范围和通道数量会反向约束芯片版图与测试结构。越早定义 wafer map、测试 coupon 和失效分档，越容易把“做出来”推进到“可筛选、可复测、可放大”。Texas announced a $24.2 million grant for FormFactor's new probe-card manufacturing facility, representing $140–170 million in planned investment. Probe pitch, contact force, pad materials, temperature range and channel count can all constrain layout and test structures, so wafer maps, test coupons and failure bins should be defined early.
一个工艺观察Process Note
量产验证要把“光—电—热—封装—测试”放进同一接口表。Production validation needs one interface table spanning optics, electricity, heat, packaging and test.
纳米结构的光学容差并不等于电学容差，晶圆厂可制造也不等于探针与封装可接入。建议用同一份接口表追踪关键尺寸、接触电阻、热路径、焊盘与对准标记、晶圆级测试条件和最终封装边界，并为每个参数指定验证阶段与责任方。Optical tolerance does not equal electrical tolerance, and foundry manufacturability does not guarantee probe or package access. Track critical dimensions, contact resistance, thermal paths, pads, alignment marks, wafer-test conditions and package boundaries in one interface table.
项目准备提醒Project Prep
提交需求时附上目标产线与测试边界。Attach target-line and test boundaries to the project brief.
至少写明目标晶圆尺寸与材料平台、最小线宽和套刻、金属与焊盘体系、工作电流/电压、允许温升、封装方式、探针 pitch、测试温度、关键性能阈值和失效分档。微纳Hub 可据此提前识别原型工艺与后续晶圆厂、封装厂和测试资源之间的接口缺口。State the target wafer size and material platform, minimum linewidth and overlay, metal and pad stack, operating current and voltage, thermal limit, package type, probe pitch, test temperature, performance thresholds and failure bins.