每日轻资讯Daily Notes
从设备扩张、量子制造到 III-V 芯粒：今天三个工程接口信号。From equipment growth and quantum manufacturing to III-V chiplets: three engineering-interface signals.
今天三条信号都在提醒：设备投入、器件性能和规模制造之间，并不会自动连成一条路。越接近工程化，越要提前定义设备能力、环境边界、键合对准和测试方法，才能让“可做”变成“可重复交付”。All three signals carry the same reminder: equipment investment, device performance and scalable manufacturing do not connect automatically. The closer a project gets to engineering, the earlier it must define tool capability, environmental limits, bonding alignment and test methods to turn feasibility into repeatable delivery.
SEMI 的设备预测显示，增长已经同时覆盖晶圆制造、测试与先进封装。SEMI’s forecast shows growth spanning wafer fabrication, test and advanced packaging.
SEMI 预计全球半导体制造设备销售额 2026 年达到 1659 亿美元、2028 年达到 2295 亿美元；2026 年晶圆厂设备、测试设备和封装设备分别预计增长 23.1%、31.0% 和 9.6%。对研发项目而言，这说明后段量测、可靠性与封装能力不应等到流片后再补，而要和前段工艺一起做资源评估。SEMI forecasts global semiconductor manufacturing equipment sales of $165.9 billion in 2026 and $229.5 billion in 2028. Wafer-fab, test, and assembly-and-packaging equipment are projected to grow 23.1%, 31.0%, and 9.6% respectively in 2026. For R&D projects, back-end metrology, reliability and packaging capacity should be assessed alongside front-end processing, not added after fabrication.
NIST 的量子制造工程中心把低温、激光等使能条件纳入规模制造问题。NIST’s quantum manufacturing center treats cryogenics and lasers as scale-up enablers.
NIST 计划首期投入 2000 万美元，由 SRI 建立量子制造工程中心，目标是消除量子组件与系统的工程和制造障碍，并推进低温系统、激光等关键使能技术。量子器件项目因此不能只报单器件指标，还应明确工作温区、热负载、光路、电连接、噪声预算和校准方式。NIST plans an initial $20 million investment for SRI to establish the Quantum Manufacturing Engineering Center, targeting engineering and manufacturing barriers in quantum components and systems, including enabling technologies such as cryogenics and lasers. A quantum-device brief therefore needs operating temperature, heat load, optical path, electrical interfaces, noise budget and calibration method—not only a device metric.
imec 的 III-V 芯粒平台把无源器件、模型、键合和射频验证放进同一集成栈。imec’s III-V chiplet platform combines passives, models, bonding and RF validation in one stack.
imec 在 300 mm 射频硅中介层上集成高密度 MIM 电容、约 300 GHz 验证的无源模型和激光辅助键合；43 颗器件的对准精度优于 600 nm、旋转误差低于 0.05°，键合后仍保持射频性能。这里真正值得借鉴的是：版图、热预算、对准公差和测试结构必须作为一个共同接口管理。On a 300 mm RF silicon interposer, imec combines high-density MIM capacitors, passive models validated around 300 GHz and laser-assisted bonding. Across 43 devices, alignment was better than 600 nm and rotational error below 0.05°, with RF performance preserved after assembly. The transferable lesson is to manage layout, thermal budget, alignment tolerance and test structures as one shared interface.
一个工艺观察Process Note
真正的工程接口，是任何一次换设备、换平台或换批次后仍能执行的参数集合。A real engineering interface survives a change of tool, platform or lot.
只写“做键合”“测低温”或“加工某层”并不足以迁移。接口至少应包含材料堆栈、前后表面状态、关键尺寸、允许热预算、对准基准、夹持禁区、测试结构和判废规则，并区分目标值、可调窗口和不可越过的硬边界。“Bond,” “test cold,” or “process this layer” is not transferable. An interface should include material stack, front- and back-surface condition, critical dimensions, thermal budget, alignment references, keep-out zones, test structures and reject rules—separating targets, tunable windows and hard limits.
项目准备提醒Project Prep
提交一页“工艺—封装—测试接口表”。Submit a one-page process–package–test interface sheet.
至少列出基底与膜层、芯片尺寸、正反面禁区、最大温度、键合材料、对准精度、引出方式、工作环境和验收项目。微纳Hub 可据此识别哪些步骤必须同平台完成、哪些公差需要预留，以及哪些测试结构应在版图阶段加入。List the substrate and films, die size, front/back keep-out zones, maximum temperature, bonding material, alignment accuracy, fan-out method, operating environment and acceptance tests. MN Fab Hub can then identify co-located steps, required tolerance margin and test structures that belong in the layout.