每日资讯Daily Notes
从 8 英寸 GaN 到原子层刻蚀分线：把工艺转移和全片验证一起规划From 8-inch GaN to atomic-layer-etch pitch splitting: plan transfer and full-wafer validation together
依据 imec 的两项公开发布整理。机构披露的研发与合作信息，与微纳Hub的项目准备建议明确区分。Based on two public imec releases. Source disclosures are kept distinct from MN Fab Hub project-preparation advice.
8 英寸 GaN：工艺转移同时覆盖外延、器件与制造接口8-inch GaN: transfer spans epitaxy, devices and manufacturing interfaces
imec 与 Polar 于 10 月 12 日公布，计划通过许可转移，把用于增强型 GaN 器件的 GaN-on-Si 工艺、器件和外延技术导入 8 英寸制造，初始聚焦 40–650 V 范围。该消息说明的是合作与技术导入方向，并非对任一项目的供货或性能承诺。On October 12, imec and Polar announced a license transfer for GaN-on-Si process, device and epitaxy technology toward 8-inch e-mode GaN manufacturing, initially focused on 40–650 V. This describes a collaboration and transfer direction, not a supply or performance promise for any project.
原子层刻蚀分线：图形密度之外还要看全片证据Atomic-layer-etch pitch splitting: density still needs full-wafer evidence
AlixLabs 于 10 月 1 日宣布在 NanoIC 中试线评估其原子层刻蚀间距分割技术；公开说明将结合先进光刻、工艺整合和量测，并以全片性能数据支撑后续资格认证。技术演示不能直接等同于量产窗口，设备、材料和图形组合仍需逐项确认。On October 1, AlixLabs announced an evaluation of atomic-layer-etch pitch splitting in the NanoIC pilot line, combining lithography, integration and metrology with full-wafer performance evidence for qualification. A technical demonstration is not automatically a production window; tool, material and pattern combinations still need confirmation.
一个工艺观察Process Note
工艺转移要有“基线晶圆—窗口—判定”的同一份证据包Keep baseline wafer, window and decision in one transfer evidence package
微纳Hub编辑观察：从宽禁带器件导入到先进图形模块验证，转移的难点不止是一段配方。应同时记录基线晶圆和外延信息、版图/掩模版本、关键设备与前处理、片内/片间取样、CD/膜厚/电性量测条件、失效模式和放行规则，避免把不同批次的读数误作同一工艺结论。MN Fab Hub editorial note: from wide-bandgap transfer to advanced patterning, the challenge is more than one recipe. Keep baseline wafer and epitaxy, layout or mask revision, tool and pre-clean, within-wafer and wafer-to-wafer sampling, CD/film/electrical conditions, failure modes and release rules together.
项目准备提醒Project Prep
先约定哪些读数决定“可以进入下一阶段”Agree which readouts permit the next stage
提交 GaN、刻蚀分线或高密度图形需求时，可先列出目标材料栈、晶圆尺寸与基底、最小线宽/间距及允许偏差、测试结构、抽样地图、目标电压或电学条件、可靠性或复测触发条件。未知项应标为待确认；不要把公开发布中的范围或路线图直接写成验收指标。微纳Hub可协助将这些内容整理为工艺与量测沟通单。For GaN, pitch splitting or dense-pattern requests, state the target stack, wafer size and substrate, minimum line/space and tolerance, test structures, sampling map, electrical conditions, and reliability or retest triggers. Mark unknowns; do not copy public ranges or roadmaps into acceptance criteria.
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