微纳Hub一站式聚合平台
专业词入口Topic Entry
引线键合不是只问“能不能打线”。芯片焊盘金属与钝化开口、基板或壳体、金线/铝线体系、键合方式、线弧空间、芯片贴装和后续电学测试会一起决定可行性。先把接口与验收拆开，才便于匹配封装资源。Wire bonding is more than asking whether a wire can be placed. Chip pads, passivation openings, substrate or package, wire system, bonding mode, loop clearance, die attach and electrical test jointly determine feasibility.
光电探测器、MEMS 与传感芯片、射频或功率器件、实验室原型、COB 小批量封装，以及需要从芯片焊盘引出到 PCB、陶瓷基板、载板或壳体的验证项目。Photodetectors, MEMS and sensor chips, RF or power devices, lab prototypes, small-batch COB packages, and projects that route chip pads to a PCB, ceramic carrier or housing.
芯片照片与尺寸、焊盘坐标和放大图、焊盘金属/厚度/开口、钝化层、基板与键合指位、键合线材偏好、最高温度、芯片贴装方式、引脚定义、测试夹具与数量。未确认项标为待封装平台确认。Provide chip photos and size, pad coordinates and close-ups, pad metal/thickness/opening, passivation, carrier and bond fingers, wire preference, temperature ceiling, die attach, pinout, test fixture and quantity.
焊盘尺寸、表面氧化或污染会影响可键合性；金属组合与工艺温度可能不兼容；线弧过高、线距过近或壳体空间不足会造成短路和扫线风险。高频、功率或热循环项目还需单独定义寄生参数、散热、拉力/推力及可靠性边界。Pad size, oxide or contamination can limit bondability; metal stacks and temperature may be incompatible; loop height, spacing and cavity clearance can create sweep or short risks. RF, power and thermal-cycle projects require separate parasitic, thermal and reliability criteria.
推荐下一步Next Step
请把芯片正反面、焊盘编号、基板焊指、期望线材/键合方式、是否需要底填或盖板、测试电流电压与交付数量放进同一份资料。微纳Hub 可协助将需求整理为可由封装平台核对的清单，不替代接收方的工艺确认、失效分析或可靠性承诺。Put chip views, pad numbering, carrier fingers, desired wire/bonding mode, underfill or lid need, electrical test conditions and quantity in one handoff. MN Fab Hub can organize the request for platform review, not replace process qualification or reliability commitments.
提交引线键合封装需求Submit wire-bonding request先统一芯片、基板、壳体和后续测试的接口信息。Align chip, carrier, housing and downstream-test interfaces first.
查看键合与封装工艺导航Open packaging route低阻连接建议预先定义探针方式、量程和四线法边界。Define probing, range and four-wire boundaries for low-resistance interconnects.
查看开尔文四线电阻测试Open four-wire test guide若需求涉及硅通孔与背面互连，应先拆分 TSV 与后段封装接口。For through-silicon interconnects, separate TSV and package interfaces early.
查看 TSV 硅通孔工艺需求Open TSV guide